1. Field of the Invention
The present invention relates to an integrated circuit in which elements formed with semiconductors are formed on a semiconductor substrate, and particularly to a DC-DC converter formed by using the integrated circuit.
2. Description of the Background Art
FIG. 5 is a diagram showing an existing DC-DC converter. The DC-DC converter 70 shown in FIG. 5 is a dropper type DC-DC converter in which an n-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used on the high side. The DC-DC converter 70 is formed by including an n-channel MOSFET 71 on the high side with a drain terminal to which an input voltage PVDD is applied, an n-channel MOSFET 72 on the low side with a drain terminal which is connected to the source terminal of the MOSFET 71, a coil 73 connected to the connecting point of the MOSFET 71 and the MOSFET 72, a capacitor 74 provided between the coil 73 and the ground GND, a bootstrap circuit 77 formed of a diode 75 and a capacitor 76, a driving circuit 78, a driving circuit 79, a level shift circuit 80 and a control circuit 81 which outputs specified signals to the level shift circuit 80 and the driving circuit 79 on the basis of an output voltage VOUT applied to the capacitor 74.
The control circuit 81 is operated with the electric potential of GND taken as a reference potential. Moreover, the level shift circuit 80, on the basis of a specified signal outputted from the control circuit 81, outputs a specified signal to the driving circuit 78. The driving circuit 78 can be formed with a circuit such as an overcurrent protection circuit provided therein and outputs a driving signal to the MOSFET 71 on the basis of the specified signal outputted from the level shift circuit 80. The driving circuit 79 outputs a driving signal to the MOSFET 72 on the basis of a specified signal outputted from the control circuit 81.
The DC-DC converter 70 switches the MOSFETs 71 and 72 to be alternately turned-on and -off to thereby make the input voltage PVDD drop to the output voltage VOUT with a specified magnitude. Namely, with the MOSFET 71 made turned-on and the MOSFET 72 made turned-off, energy is stored in the coil 73. With the MOSFET 71 made turned-off and the MOSFET 72 made turned-on, the energy stored in the coil 73 is released. By adjusting the respective duty ratios for which the MOSFET 71 and 72 are turned-on and -off, the energy stored in the coil 73 is controlled to make the output voltage VOUT equal to a target voltage.
In the DC-DC converter 70, the use of the n-channel MOSFET 71 on the high side necessitates applying a voltage higher than the input voltage PVDD to the driving circuit 78 when driving the MOSFET 71. Therefore, in the DC-DC converter 70, to apply a voltage higher than the input voltage PVDD to the driving circuit 78, the bootstrap circuit 77 is used. The bootstrap circuit 77 is a circuit that gives an approximately constant voltage to the driving circuit 78 with the electric potential of the source electrode of the MOSFET 71 (the electric potential of the point M shown in shown in FIG. 5) taken as a reference potential. In FIG. 5, a frame A marked by a broken line shows a module that can be formed as an integrated circuit.
Circuit elements such as resistors and capacitors formed in an integrated circuit are formed on a semiconductor substrate by using a semiconductor such as polysilicon. FIG. 6 is a diagram showing an existing integrated circuit. In the circuit configuration shown in FIG. 6, the same constituents as those shown in FIG. 5 are designated by the same reference numerals and signs as those in FIG. 5.
An integrated circuit 82 shown in FIG. 6, is formed by including a p-type semiconductor substrate 83, a resistor 85 formed on the semiconductor substrate 83 with a polysilicon film 84, a capacitor 88 formed on the semiconductor substrate 83 by polysilicon films 86 and 87 and an insulator layer (not shown) between them. The semiconductor substrate 83 is to be connected to ground GND, an n-type semiconductor layer 89 is selectively formed on the top surface of the semiconductor substrate 83, and further, a p-type semiconductor layer 90 is selectively formed on the surface of the semiconductor layer 89. Moreover, one of the terminals (the point BOOT also shown in FIG. 5) of the capacitor 76 is connected to the semiconductor layer 89, and the other terminal (the point M also shown in FIG. 5) of the capacitor 76 is connected to the semiconductor layer 90. In addition, although not shown in FIG. 6, besides the resistor 85 and the capacitor 88, the elements such as the MOSFETs 71 and 72 and the driving circuits 78 and 79 are also to be formed in the integrated circuit 82.
In thus formed integrated circuit 82, as shown in FIG. 6, parasitic capacitance 91 is adjunctively formed to some extent between the semiconductor substrate 83 and the resistor 85 and between the semiconductor substrate and the capacitor 88.
The parasitic capacitance 91 causes two problems. The first one is that noise accompanying operation of a number of circuit elements formed on the semiconductor substrate 83 and noise superimposed on a power source voltage supplied externally enter the resistor 85, the capacitor 88 and the driving circuits 78 and 79 from the semiconductor substrate 83 through the parasitic capacitance 91.
The second problem occurs when the driving circuit 78 shown in FIG. 5 is formed by using the resistor 85 and the capacitor 88 in the integrated circuit 82, for example. The problem is that each change in the electric potential at the point M accompanied by the turning on-and-off operation of the MOSFETs 71 and 72 (the electric potential at the point BOOT as the potential of the power source for the driving circuit 78 also changes with the change at the point M) causes large noise signals, equivalent to a voltage applied with an amplitude between the input voltage PVDD and GND, to enter the driving circuit 78, with the parasitic capacitance 91 made functioned as a coupling capacitance, which may prevent normal operation of the DC-DC converter 70.
To counteract the first problem, there is a proposal in which a shielding layer of an n-type semiconductor is provided in each of the region between the semiconductor substrate 83 and the resistor 85 and the region between the semiconductor substrate 83 and the capacitor 88, and the shielding layer is connected to the power source or GND at a fixed electric potential to thereby shield the resistor 85 and the capacitor 88 from noise from the semiconductor substrate 83 (see JP-A-7-30064 (paragraphs 0010 to 0012, and FIG. 1) or JP-A-63-29962 (pages 3 to 4, and FIGS. 1 to 3, 5 and 6), for example)).
However, the arrangement proposed in JP-A-7-30064 or JP-A-63-29962, in which a shielding layer is provided in each of the region between the semiconductor substrate 83 and the resistor 85 and the region between the semiconductor substrate 83 and the capacitor 88 and, along with this, the shielding layer is connected to the power source or GND, can only deal with the first problem but can not solve the second problem. Specifically, there is no difference between the proposed arrangement and that of the existing one in as much as a coupling capacitance is present between a circuit with its reference potential changed and a region at a fixed electric potential (the semiconductor substrate). Therefore, a large amount of noise enters the driving circuit 78 along with the switching operation of the MOSFETs 71 and 72.
Accordingly, the invention has an object of providing an integrated circuit that can solve the two problems caused by the parasitic capacitance between the semiconductor substrate and the elements, particularly the second problem, which could not previously be solved, and a DC-DC converter formed by using such an integrated circuit.